From January 2025, TSMC will raise the OEM price of 3nm, 5nm and CoWoS processes, and the increase is expected to be between 5% and 20%.
CoWoS may experience a simultaneous increase in volume, price, and demand, with a clear trend of CoWoS-S shifting towards CoWoS-L. In terms of quantity, according to DIGITIMES Research data, driven by strong demand for cloud AI accelerators, the global demand for CoWoS and similar packaging capacity is expected to increase by 113% by 2025. The main suppliers, TSMC, Sunlight Technology Holdings (including Silicon Precision Industries, SPIL), and Ankao, are expanding their production capacity. According to the DIGITIME SR research report, by the end of the fourth quarter of 2025, TSMC’s monthly production capacity is expected to increase to over 65000 12 inch wafer equivalents, while the combined production capacity of AnKou and Sunlight will increase to 17000 wafers; Nvidia is TSMC’s largest customer for CoWoS packaging technology. Benefiting from Nvidia’s Blackwell series GPU mass production, TSMC will transition from CoWoS-S to CoWoS-L process starting from the fourth quarter of 2025, making CoWoS-L the main process for TSMC’s CoWoS technology; Nvidia’s demand for CoWoS-L process may significantly increase from 32000 wafers in 2024 to 380000 wafers in 2025, a year-on-year increase of 1018%.
According to DIGITIME Research, CoWoS-L is expected to account for 54.6% of TSMC’s total CoWoS production capacity, CoWoS-S for 38.5%, and CoWoS-R for 6.9% in the fourth quarter of 2025. In terms of price, according to data from Semiconductor Manufacturing Network, the prices of TSMC’s 3nm and 5nm process technologies will increase by 5% to 10%, and the CoWoS process will increase by 15% to 20% (in short supply). This adjustment is not only due to the surge in demand for computing power in the AI field, but also reflects the continuous rise in process technology costs. In terms of demand, according to semiconductor vertical and horizontal data, Nvidia accounts for over 50% of the overall supply of CoWoS, A100、 In the first half of the year, products such as 00 and Blackwell Ultra will use CoWoS packaging. In 2025, Nvidia will promote the B300 and GB300 series using CoWoS-L technology. AMD’s MI300 adopts two packaging technologies, TSMC SoIC (3D) and CoWoS (2.5D). In addition, Broadcom, Microsoft, Amazon, and Google also have certain demands for CoWoS.
CoWoS-L ensures good system performance while avoiding yield loss of large silicon interlayers. The CoWoS-L intermediate layer includes multiple local silicon interconnect (LSI) chips and a global redistribution layer (RDL), forming a recombination intermediate layer (RI) to replace the monolithic silicon intermediate layer in CoWoS-S. Compared with CoWoS-S, LSIChiplet retains sub micron level copper interconnects, through silicon vias (TSV), and embedded deep trench capacitors (eDTC) to ensure good system performance while avoiding yield loss issues in large silicon interlayers. In addition, introducing through insulator vias (TIVs) as vertical interconnects in RI provides a lower insertion loss path than TSV. CoWoS-L has successfully implemented a plug with a 3x mask size (approximately 2500 square millimeters), equipped with multiple SoC/chip modules and 8 HBM solutions. There are two routes for LSI manufacturing, LSI-1 and LSI-2, with the main difference being the interconnect metal scheme: when manufacturing LSI-1, TSV and a layer of single Damascus copper metal (M1) are first fabricated on a 300mm silicon chip. Then, a double Damascus copper interconnect structure was formed using undoped silicate glass (USG) as the dielectric layer. In the LSI-1 metal scheme, the minimum metal width/space provided by the dual Damascus copper process is 0.8 and 0.8 μ m, with a thickness of 2 μ m; LSI-2 has the same TSV structure and M1 metal scheme. After manufacturing the M1 layer, a semi additive process (SAP) is used to form an interconnect structure of copper RDL with polyimide (PI) as the dielectric layer. The minimum width/space of SAP copper RDL is 2.2 μ m, and the thickness is 2.3 μ m.